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A 1 GOPS reconfigurable signal processing IC with embedded FPGA and 3-port 1.2 GB/s flash memory subsystem

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10 Author(s)
M. Borgatti ; STMicroelectronics, Agrate Brianza, Italy ; L. Call ; G. De Sandre ; B. Foret
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A 1 GOPS dynamically reconfigurable processing unit with embedded flash memory and SRAM-based FPGA for image/voice processing/recognition applications is described. Code, data and FPGA bitstreams are stored in the embedded flash memory and are independently accessible through 3 content-specific, 64 b I/O ports with a peak read rate of 1.2 GB/s. The system is implemented in a 0.18 /spl mu/m 2P 6M CMOS flash technology with a chip area of 70 mm/sup 2/.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003