A 51.2 GOPS fully programmable and scalable video recognition processor is based on a linear connection of 128 4-way VLIW processing elements and an asynchronous data mapping mechanism. Execution is under 33 ms/frame for complex weather, robust road area/lane marking, and vehicle detection. The chip contains 32.7M transistors in 121 mm2 area fabricated in 0.18 μm 7M CMOS.
Published in:
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Date of Conference: 2003