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A 51.2 GOPS fully programmable and scalable video recognition processor is based on a linear connection of 128 4-way VLIW processing elements and an asynchronous data mapping mechanism. Execution is under 33 ms/frame for complex weather, robust road area/lane marking, and vehicle detection. The chip contains 32.7M transistors in 121 mm2 area fabricated in 0.18 μm 7M CMOS.
Date of Conference: 2003