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Image processor capable of block-noise-free JPEG2000 compression with 30 frames/s for digital camera applications

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12 Author(s)
H. Yamauchi ; Sanyo Electr. Co. Ltd., Gifu, Japan ; S. Okada ; K. Taketa ; T. Ohyama
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A one-chip image processor for next-generation digital cameras and broadband PDA multimedia mobile phones is described. It is capable of processing JPEG2000 data with 30 frames/s and a 27 MHz operating frequency. The process is fabricated in 0.25 /spl mu/m CMOS and contains 8.5M transistors in a 103 mm/sup 2/ area.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003