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A 160 mW, 80 nA standby, MPEG-4 audiovisual LSI with 16 Mb embedded DRAM and a 5 GOPS adaptive post filter

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18 Author(s)
Arakida, H. ; Toshiba Corp., Kawasaki, Japan ; Takahashi, M. ; Tsuboi, Y. ; Nishikawa, T.
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A single-chip MPEG-4 audiovisual LSI in a 0.13 /spl mu/m 5M CMOS technology with 16 Mb embedded DRAM is presented. Four 16 b RISC processors and dedicated hardware accelerators including a 5 GOPS post filtering engine are integrated on the IC. The chip consumes 160 mW at 125 MHz and uses 80 nA in the standby mode. This LSI handles MPEG-4 CIF video encoding at 15 frames/s and audio encoding simultaneously.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003