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Sorting with linear speedup on a pipelined hypercube

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2 Author(s)
P. J. Varman ; Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA ; K. Doshi

The authors formally define a distributed-memory parallel architecture called the pipelined hypercube. A coarse-grained parallel sorting algorithm that can be mapped efficiently on such an architecture is also presented. The pipelined hypercube has a more powerful communication mechanism than the traditional binary code architecture, in that it permits communication of blocks of data between processing elements (PEs) to be performed in a pipelined manner. Certain data communication problems which would probably be serialized on the binary code architecture, can be performed optimally on the pipelined hypercube. The sorting algorithm can be mapped efficiently onto a pipelined hypercube of P PEs. It sorts N data items, initially distributed among the PEs, in time O((N log N/P)+log2 P), thereby achieving linear speedup when P is O(N/log N)

Published in:

IEEE Transactions on Computers  (Volume:41 ,  Issue: 1 )