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Concurrent transient fault simulation for analog circuits

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2 Author(s)
Junwei Hou ; Cadence Design Syst. Inc., San Jose, CA, USA ; A. Chatterjee

This paper presents a novel concurrent fault simulation algorithm for nonlinear analog circuits. Between successive time steps in transient fault simulation, all faulty circuits in the fault list are simulated before the simulator proceeds to the next step. Four primary techniques, including fault grouping, fault ordering, state prediction, and reduced-order fault matrix computation, are proposed to significantly reduce analog fault simulation complexity by making use of the similarities between the faulty and fault-free circuits. The method has been implemented in a dc and transient fault simulator called CONCERT2, which is the first ever for nonlinear analog circuits. Up to two orders of magnitude speedup is obtained for complete transient fault simulation, without loss of accuracy in fault detection. It is shown that the methodology of CONCERT2 can significantly speed up the process of analog test stimulus generation.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:22 ,  Issue: 10 )