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The challenges for developing an on-chip electrostatic discharge (ESD) protection circuit layout extractor originate from unconventional layout patterns of ESD protection devices, parasitic ESD device extraction, and device count reduction. This paper reports a new technology independent layout extractor called the ESDExtractor, which is capable of extracting arbitrary ESD protection devices and answers the demands for full-chip ESD protection design verification. The general methodology to extract both intentional and parasitic ESD protection devices, the specific algorithms, and implementation methods to enhance ESDExtractor's efficiency are presented. Finally, the capability of the new computer-aided design tool is demonstrated using application examples.