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A 1-V 2.5-mW 5.2-GHz frequency divider in a 0.35-μm CMOS process

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3 Author(s)
J. M. C. Wong ; Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China ; V. S. L. Cheung ; H. C. Luong

A 1-V low-power high-speed dynamic-loading frequency divider is proposed using novel D flip-flops with a common-gate topology and with a single clock phase. A simple and accurate small-signal analysis model is provided to estimate the operating frequencies of the divider. Implemented in a standard digital 0.35-μm CMOS process and at 1-V supply, the proposed frequency divider measures a maximum operating frequency up to 5.2 GHz with a power consumption of 2.5 mW.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:38 ,  Issue: 10 )