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Low-power fully integrated 10-Gb/s SONET/SDH transceiver in 0.13-μm CMOS

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12 Author(s)
L. Henrickson ; Agere Syst., Santa Clara, CA, USA ; D. Shen ; U. Nellore ; A. Ellis
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Here, we present a low-power fully integrated 10-Gb/s transceiver in 0.13-μm CMOS. This transceiver comprises full transmit and receive functions, including 1:16 multiplex and demultiplex functions, high-sensitivity limiting amplifier, on-chip 10-GHz clock synthesizer, clock-data recovery, 10-GHz data and clock drivers, and an SFI-4 compliant 16-bit LVDS interface. The transceiver exceeds all SONET/SDH (OC-192/STM-64) jitter requirements with significant margin: receiver high-frequency jitter tolerance exceeds 0.3 UIpp and transmitter jitter generation is 30 mUIpp. All functionality and specifications (core and I/O) are achieved with power dissipation of less than 1 W.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:38 ,  Issue: 10 )