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Simulation of nanofloating gate memory with high-k stacked dielectrics

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4 Author(s)
Govoreanu, B. ; SPDT Div., IMEC, Leuven, Belgium ; Blomme, P. ; Van Houdt, J. ; de Meyer, K.

Scaling of conventional floating gate nonvolatile memory cells towards the nanometer range is jeopardized by the lack of scalability of the tunnel oxide. In this paper, we discuss the advantages of using high-k materials for nanofloating gate memory structures by means of numerical device simulations.

Published in:

Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on

Date of Conference:

3-5 Sept. 2003