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Optimization of L/sub Gate/ for ggNMOS ESD protection devices fabricated on bulk- and SOI- substrates, using process and device simulation

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2 Author(s)
Deckelmann, A.I. ; Inst. for Phys. of Electrotechnol., Munich Univ. of Technol., Germany ; Wachutka, G.

The high-current characteristics of ggNMOS fabricated on bulk- as well as on SOI-substrates using a 0.6 /spl mu/m-CMOS technology have been simulated for different values of the gate length L/sub Gate/. Prior to the simulation, the doping profiles and physical transport parameters were calibrated with reference to measured data. The snapback differential resistance R/sub spdiff/ is found to be higher for SOI-devices. Also, an optimum value of L/sub Gate/ is determined for the bulk-substrate, yielding a minimum snapback holding voltage V/sub H/. For SOI fabrication, however, VH decreases with shrinking L/sub Gate/. We explain this behavior on the basis of the electrothermal simulation results.

Published in:

Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on

Date of Conference:

3-5 Sept. 2003