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ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness

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3 Author(s)
Ming-Dou Ker ; Nanoelectronics & Gigascale Syst. Lab., Nat. Chiao-Tung Univ., Hsinchu, Taiwan ; Hsin-Chyh Hsu ; Jeng-Jie Peng

A new electrostatic discharge (ESD) implantation method is proposed to significantly improve ESD robustness of CMOS integrated circuits in subquarter-micron CMOS processes, especially the machine-model (MM) ESD robustness. By using this method, the ESD current is discharged far away from the surface channel of nMOS, therefore the nMOS (both single nMOS and stacked nMOS) can sustain a much higher ESD level. The MM ESD robustness of the gate-grounded nMOS with a device dimension width/length (W/L) of 300 μm/0.5 μm has been successfully improved from the original 450 V to become 675 V in a 0.25-μm CMOS process. The MM ESD robustness of the stacked nMOS in the mixed-voltage I/O circuits with a device dimension W/L of 300 μm/0.5 μm for each nMOS has been successfully improved from the original 350 V to become 500 V in the same CMOS process. Moreover, this new ESD implantation method with the n-type impurity can be fully merged into the general subquarter-micron CMOS processes.

Published in:

IEEE Transactions on Electron Devices  (Volume:50 ,  Issue: 10 )