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Unified theory to build cell-level transistor networks from BDDs [logic synthesis]

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4 Author(s)
Poli, R.E.B. ; Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil ; Schneider, F.R. ; Ribas, R.P. ; Reis, A.I.

This paper presents a unified theory to build transistor networks through binary decision diagrams - BDDs. It is able to obtain transistor networks with transistor count near to the best case of other methods presented in the literature. As a result, a pass transistor network implementation is automatically generated for XOR-like gates, since static CMOS performs badly. Similarly, a static CMOS topology is preferred for the generation of NAND-like gates, on which pass transistor logic is not optimal. Variations on the derivation of transistor networks from BDDs are extensively discussed.

Published in:

Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th Symposium on

Date of Conference:

8-11 Sept. 2003