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This paper presents generalized structures to design 1-of-M QDI (quasi delay-insensitive) asynchronous adders. These structures allow one to design from simple ripple-carry adders to faster parallel-prefix adders. The proposed method is fully automated and integrated in the TAST (TIMA asynchronous synthesis tool) tools suite. This work also demonstrates that the most widely used dual-rail encoding (binary representation in QDI circuits) is not the best solution for number representation in asynchronous circuits. According to the domain of values to be represented, increasing the base leads to parallel-prefix adders with lower area, delay and power consumption. Hence, this work enables the designer to optimize his/her design by choosing the appropriated 1-of-M number representation.