A fast IP-core integration methodology for SoC design

The system on a chip (SoC) has become a reality, hosting the design of complex circuits into a single programmable device, supporting different cores for microprocessors, interfaces, buses, etc. However, the automatic inclusion of new general cores, from different providers, via a standard bus still needs a reliable interface mechanism to guarantee the correct protocol conversion and performance. This work presents a CAD tool to cope with this problem, based on a Petri net protocol conversion approach in a high level behavioral specification, focusing on bus planning and core integration.