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Digital video compression is a computationally intensive task, in which motion estimation accounts for a significant portion of the arithmetic operations. This paper presents ME64, a dedicated scalable hardware architecture for fast computation of motion vectors. ME64 is a highly parallel architecture, based on a matrix of 64 processing elements at its core, an I/O interface, and comparison and control units. The proposed architecture was implemented in an FPGA to treat reference and search blocks of 8×8 and 15×15 pixels, respectively. ME64 is scalable to be able to cover larger search blocks if needed. It implements the full search algorithm using the SAD criteria. ME64 was fully described in VHDL and prototyped in the Xilinx XC2S150 FPGA device, with a maximum frequency of 33 MHz. Using this FPGA device, ME64 reaches 2.1 GOps (billions of 8-bit operations per second) and 107.32 frames (640×480 pixels) per second. The results herein presented validate the ME64 against a software implementation, using an external I/O data driver.