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Towards a high-level synthesis of reconfigurable bit-serial architectures

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4 Author(s)
A. Rettberg ; Paderborn Univ., Germany ; F. Dittmann ; M. Zanella ; T. Lehmann

This paper presents high-level synthesis methods for a fully reconfigurable self-timed synchronous bit-serial pipeline architecture. The idea is to distribute the central control unit. Local controls of the operators are realized through a one-shot implementation of the central control engine. Specialized routing components allow the reconfiguration of the implemented circuit with respect to rapid system prototyping. We describe several kinds of high-level synthesis approaches, especially the scheduling, which can be used for this type of architecture. This means we optimize specific characteristics, like loops, junctions and splitters, during the synthesis phase.

Published in:

Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th Symposium on

Date of Conference:

8-11 Sept. 2003