By Topic

Novel approach to the design of direct digital frequency synthesizers based on linear interpolation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Langlois, J.M.P. ; Dept. of Electr. & Comput. Eng., R. Mil. Coll. of Canada, Kingston, Ont., Canada ; Al-Khalili, D.

This paper presents a novel approach to the design of direct digital frequency synthesizers (DDFSs) with phase-to-sinusoid amplitude conversion blocks based on linear interpolation. For such DDFSs, the first quadrant of the sine function is approximated with a number of linear segments. Simple control circuitry reconstructs a full sine wave by symmetry. DDFS architectures using linear interpolation are first discussed, and an analysis of their spectral properties is given. From this analysis, an upper bound is provided for the spurious free dynamic range (SFDR) that can be attained for a given number of linear segments. A detailed and systematic procedure for the selection of linear segment coefficients achieving a desired SFDR is then proposed. A generalized multiplierless linear interpolation DDFS architecture is described, and specific designs achieving 84 and 96 dBc of SFDR are discussed and compared with previous work. It is shown that the complexity of synthesizers based on the new approach, in terms of the number of transistors and silicon area, is significantly less than that of previously presented DDFS designs of similar performance.

Published in:

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:50 ,  Issue: 9 )