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High-frequency, at-speed scan testing

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7 Author(s)
Xijiiang Lin ; Design-for-Test Products Group, Mentor Graphics Corp., Beaverton, OR, USA ; R. Press ; J. Rajski ; P. Reuter
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The authors describe new strategies where at-speed scan tests can be applied with internal PLL. They present techniques for optimizing ATPG across multiple clock domains and methodologies to combine both stuck-at-fault and delay-test vectors into an effective test suite.

Published in:

IEEE Design & Test of Computers  (Volume:20 ,  Issue: 5 )