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A low-cost test solution for wireless phone RFICs

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4 Author(s)

This article describes an IBM approach for testing high-volume, complex RFICs at a fraction of the cost of the integrated circuit. This approach uses a personal computer, a fast benchtop dc parametric analyzer, and RF-to-analog circuits to test an RFIC during the manufacturing process. The described system and methodology are specifically designed for high-volume test, where test cost is extremely important; they are not recommended for lower-volume products (less than 1 million per month). This article describes the system architecture and discusses design, maintenance, and implementation considerations. The system is designed to reduce the cost of a complex RFIC manufacturing test to equal that of a discrete component, such as a resistor or capacitor. Given the relatively easy implementation and the drastic cost reduction associated with the test solution, this architecture establishes a new standard for the future of RF test. In fact, this architecture may result in the fastest RF tester currently available.

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Communications Magazine, IEEE  (Volume:41 ,  Issue: 9 )