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Back-end dynamic resource allocation heuristics for power-aware high-performance clustered architectures

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1 Author(s)
Baniasadi, A. ; Electr. & Comput. Eng., Univ. of Victoria, BC, Canada

In this paper, we present dynamic resource allocation heuristics for high-performance clustered processors. Our heuristics aim at saving power by reducing processor back-end size dynamically and at a cluster level. This is done by shutting down or gating one of the clusters in a multi-cluster processor occasionally. Key to success of our heuristics is power-efficient techniques that could identify when a processor back-end could be downsized safely (i.e., without performance cost). We suggest techniques that do so by estimating a) branch confidence b) the available instruction level parallelism (ILP), and c) instruction flow. We show that, on the average, our methods reduce total power dissipation 14% and 11% for a subset of SPEC2K benchmarks and for dual and quad cluster processors. Our techniques improve performance for some benchmarks since they reduce the number of cluster-induced stalls. However, our best techniques come with an average performance loss of 1.1% for dual cluster processors. The lowest average performance cost is 0.9% for quad cluster processors.

Published in:

Digital System Design, 2003. Proceedings. Euromicro Symposium on

Date of Conference:

1-6 Sept. 2003