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Modeling and estimation of total leakage current in nano-scaled-CMOS devices considering the effect of parameter variation

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2 Author(s)
S. Mukhopadhyay ; Dept. of ECE, Purdue Univ., West Lafayette, IN, USA ; K. Roy

In this paper we have developed analytical models to estimate the mean and the standard deviation in the gate, the subthreshold, the reverse biased source/drain junction band-to-band tunneling (BTBT) and the total leakage in scaled CMOS devices considering variation in process parameters like device geometry, doping profile, flat-band voltage and supply voltage. We have verified the model using Monte Carlo simulation using an NMOS device of 50 nm effective length and analyzed the results to enumerate the effect of different process parameters on the individual components and the total leakage.

Published in:

Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on

Date of Conference:

25-27 Aug. 2003