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Multi-threshold CMOS is a popular technique for reducing standby leakage power with low delay overhead. MTCMOS designs typically use large sleep devices to reduce standby leakage at the block level. We provide a formal examination of sneak leakage paths and a design methodology that enables gate-level insertion of sleep devices for sequential and combinational circuits. A fabricated 0.13 μm, dual VT test chip employs this methodology to implement a low-power FPGA core with gate-level sleep FETs and over 8× measured standby current reduction. The methodology allows local sleep regions that reduce leakage in active configurable logic blocks (CLBs) by up to 2.2× (measured) for some CLB configurations.