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Carbon Nanotube Field-Effect Transistors (CNFETs) are being extensively studied as possible successors to CMOS. Novel device structures have been fabricated and device simulators have been developed to estimate their performance in a sub-10 nm transistor era. This paper presents a novel circuit-compatible modeling of CNFETs in their ultimate performance limit. The model so developed has been used to simulate arithmetic and logic blocks using HSPICE.
Nanotechnology, 2003. IEEE-NANO 2003. 2003 Third IEEE Conference on (Volume:1 )
Date of Conference: 12-14 Aug. 2003