Debug architecture for system on chip taking full advantage of the test access port

This paper describes the architecture of a structural, cost effective debug methodology, applicable to a system on chip in its system environment and targeting software as well as hardware debugging. The highly modular and flexible architecture enables an almost infinite variation of flexible configurable modules designed and hooked up to the test access port (TAP). The hardware configuration flexibility is supported by software running on a PC or workstation, hooked up via a POD connected to the TAP interface. The result is an easy to use implementation of increased observability.