By Topic

Automatic worst case pattern generation using neural networks & genetic algorithm for estimation of switching noise on power supply lines in CMOS circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Liau, E. ; MP Technol. & Innovation, Infineon Technol. AG, Munich, Germany ; Schmitt-Landsiedel, D.

In our approach, we use ATE (automatic test equipment) to teach a neural network (NN) to correctly classify a set of worst case input patterns with respect to the maximum instantaneous current. This can be thought of as learning a behavior of chip power consumption change due to different input patterns applied. We then further optimize this set of (NN) worst case patterns using a genetic algorithm (GA). The final set of worst case patterns can efficiently identify a defective or weakness due to power supply noise as well as locate the defect or weakness within the design. To the best of our knowledge, this is the first NN learning and GA self-optimization ATE-based approach for practical application in silicon analysis automation. Our practical experimental results demonstrate the enlarged fault coverage obtained with this approach.

Published in:

Test Workshop, 2003. Proceedings. The Eighth IEEE European

Date of Conference:

25-28 May 2003