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Test application time and core accessibility are two major issues in system-on-chip (SoC) testing. The test application time must be minimised and a test access mechanism (TAM) must be developed to transport test data to and from the cores. In this paper, we present an approach to design a core level test interface (wrapper) taking into account the P1500 restrictions, and to design a TAM architecture and its associated test schedule using a fast and efficient heuristic. A useful and new feature of our approach is that it also supports the testing of interconnections while considering power dissipation, test conflicts and precedence constraints. Another feature of our approach is that the TAM is designed with a central bus architecture, which is a generalisation of the TestBus architecture. The advantages and drawbacks of our approach are discussed and the proposed architecture and heuristic are validated with experiments.