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Multistage interconnection networks for parallel Viterbi decoders

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4 Author(s)
Akopian, D. ; Nokia Corp., Tampere, Finland ; Takala, J. ; Saarinen, J. ; Astola, J.

We propose new multistage interconnection networks (MIN) for scalable parallel Viterbi decoder architectures. The architecture consists of the desired number of processing elements (PE) connected by the suggested MINs, thus allowing a tradeoff between complexity and speed. The structure of the MIN is derived first by transforming the de Bruijn interconnection-based Viterbi algorithm trellis into the equivalent trellis with a perfect shuffle interconnection, and then applying a new decomposition of the perfect shuffle operator. This results in an efficient modular system and data flow is formed by the shuffling in a local PE memory and data exchange through a fixed interconnection between PEs. We suggest several solutions for 1/n and k/n rate codes, where k denotes the number of input bits shifting into k shift registers of the encoder and, at each cycle, the encoder produces n output bits as linear combinations of certain bits in the shift registers.

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Communications, IEEE Transactions on  (Volume:51 ,  Issue: 9 )