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Novel electrostatic discharge protection design for nanoelectronics in nanoscale CMOS technology

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2 Author(s)
Ming-Dou Ker ; Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Tang-Kui Tseng

A novel electrostatic discharge (ESD) protection concept by using the already-on device is proposed to effectively protect CMOS integrated circuits (IC) in nanoscale CMOS processes against ESD stress. Such an already-on NMOS device is designed to have a threshold voltage of ∼0 V, or even negative. When the IC is under the ESD zapping conditions, such already-on NMOS in CMOS IC are initially standing in the turn-on state and ready to discharge ESD current during any ESD zapping. So, such already-on NMOS has the fastest turn-on speed and the lowest trigger-on voltage to effectively protect the internal circuits with a much thinner gate oxide (∼15 Å) in future sub-100 nm CMOS technology. To keep such already-on devices off when the IC is under normal circuit operating condition, an on-chip negative voltage generator realized by the diodes and capacitors is used to bias the gates of such already-on devices. The proposed already-on device and the on-chip negative voltage generator are fully process-compatible to the general sub-100 nm CMOS processes.

Published in:

Nanotechnology, 2003. IEEE-NANO 2003. 2003 Third IEEE Conference on  (Volume:2 )

Date of Conference:

12-14 Aug. 2003