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Background charge insensitive single electron memory devices

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4 Author(s)
K. K. Yadavalli ; Dept. of Electr. Eng., Notre Dame Univ., IN, USA ; A. O. Orlov ; G. L. Snider ; A. N. Korotkov

We present an overview of the experiments on lateral gap floating gate single electron memory cells with different gaps between the floating gate and the control gate. Charging of the floating gate is observed in these devices. A background charge insensitive mode of operation is demonstrated in a device, with a bit of information represented by about 20 electrons. Experiments are performed to understand charging at high bias in large gaps, and a charge trapping network is proposed to account for the observed results. A fabrication process for stacked geometry devices is developed involving oxide growth in oxygen plasma. Initial experiments indicate the feasibility of using this method to fabricate memory cells with precise tunnel barriers.

Published in:

Nanotechnology, 2003. IEEE-NANO 2003. 2003 Third IEEE Conference on  (Volume:2 )

Date of Conference:

12-14 Aug. 2003