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Stochastic assembly of sublithographic nanoscale interfaces

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3 Author(s)
DeHon, A. ; Dept. of Comput. Sci., California Inst. of Technol., Pasadena, CA, USA ; Lincoln, P. ; Savage, J.E.

We describe a technique for addressing individual nanoscale wires with microscale control wires without using lithographic-scale processing to define nanoscale dimensions. Such a scheme is necessary to exploit sublithographic nanoscale storage and computational devices. Our technique uses modulation doping to address individual nanowires and self-assembly to organize them into nanoscale-pitch decoder arrays. We show that if coded nanowires are chosen at random from a sufficiently large population, we can ensure that a large fraction of the selected nanowires have unique addresses. For example, we show that N lines can be uniquely addressed over 99% of the time using no more than 2.2log2(N)+11 address wires. We further show a hybrid decoder scheme that only needs to address N=O(Wlitho-pitch/Wnano-pitch) wires at a time through this stochastic scheme; as a result, the number of unique codes required for the nanowires does not grow with decoder size. We give an O(N2) procedure to discover the addresses which are present. We also demonstrate schemes that tolerate the misalignment of nanowires which can occur during the self-assembly process.

Published in:

Nanotechnology, IEEE Transactions on  (Volume:2 ,  Issue: 3 )

Date of Publication:

Sept. 2003

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