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Design of a cycle-efficient 64-b/32-b integer divisor using a table-sharing algorithm

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4 Author(s)
Chua-Chin Wang ; Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan ; Po-Ming Lee ; Jun-Jie Wang ; Chenn-Jung Huang

In new generations of microprocessors, the superscalar architecture is widely adopted to increase the number of instructions executed in one cycle. The division instruction among all of the instructions needs more cycles than the rest, e.g., addition and multiplication. This makes the division instruction an important cycles-per-instruction figure for modern microprocessors. In this paper, a radix-16/8/4/2 divisor is proposed, which uses a variety of techniques, including operand scaling, table partitioning, and, particularly, table sharing, to increase performance without the cost of increasing complexity. A physical chip using the proposed method is implemented by 0.35-/spl mu/m single poly four metal (1P4M) CMOS technology. The testing measurement shows that the chip can execute signed 64-b/32-b integer division between 3-13 cycles with a 80-MHz operating clock.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:11 ,  Issue: 4 )