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The high overhead of generic protocols like TCP/IP provides strong motivation for the development of a better protocol architecture for cluster-based parallel computers. Reconfigurable computing has a unique opportunity to contribute hardware level protocol acceleration while retaining the flexibility to adapt to changing needs. Thus, it is possible to provide application-specific protocol processing to improve performance and to reduce space utilization. Reducing space utilization permits the use of a greater portion of the FPGA for other application-specific processing. This paper focuses on work to create a set of components that can be put together as needed to obtain a customized protocol for each application. The components are parameterizable, increasing the protocol's flexibility. To study the feasibility of such an architecture, hardware components for the reconfigurable logic on the NIC were built such that they can be stitched together as required to provide the required functionality. Feasibility is demonstrated using four different protocol configurations in this paper. The different configurations illustrate trade-offs between chip space and functionality.