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Use of hand optimized Intellectual Property (IP) logic cores is prolific in hardware design. These IP cores range from rather complicated signal processing transforms and filters to arithmetic operators. While IP cores remain a standard way to utilize the improvement in FPGA technology and contend with time to market pressure through reuse, popularity of tools generating hardware descriptions from high-level languages is increasing in popularity. The PACT HDL behavioral synthesis tool attempts to combine these two methods within a power-aware framework. PACT HDL generates RTL HDL codes in VHDL and Verilog using a finite state machine (FSM) style. These codes use intrinsic operators to represent calculations such as addition, subtraction, and multiplication. The output HDL codes are passed to commercial RTL synthesis tools that generate the gate-level hardware descriptions. Each intrinsic operator is replaced with a hardware implementation of the calculation by the synthesis tool. Unfortunately, by leaving this decision to the synthesis tool, the gate-level instantiation may not be appropriate for the desired constraints, particularly those relating to power consumed. The synthesis tools tend to use combinational implementations that are area and power hungry. In some cases, the tool may not be able to instantiate the appropriate logic, such as the division operator, at all.