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The reliability of FPGA circuit designs in the presence of radiation induced configuration upsets

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5 Author(s)
M. Wirthlin ; Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA ; E. Johnson ; N. Rollins ; M. Caffrey
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FPGAs are an appealing solution for space-based remote sensing applications. However, in a low-Earth orbit, FPGAs (field programmable gate arrays) are susceptible to Single-Event Upsets (SEUs). In an effort to understand the effects of SEUs, an SEU simulator based on the SLAAC-1V computing board has been developed. This simulator artificially upsets the configuration memory of an FPGA and measures its impact on FPGA designs. The accuracy of this simulation environment has been verified using ground-based radiation testing. This simulation tool is being used to characterize the reliability of SEU mitigation techniques for FPGAs.

Published in:

Field-Programmable Custom Computing Machines, 2003. FCCM 2003. 11th Annual IEEE Symposium on

Date of Conference:

9-11 April 2003