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System level power-performance trade-offs in embedded systems using voltage and frequency scaling of off-chip buses and memory

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6 Author(s)
Puttaswamy, K. ; Center for Res. in Embedded Syst. & Technol., Georgia Inst. of Technol., Atlanta, GA, USA ; Kyu-won Choi ; Jun Cheol Park ; Mooney, V.J., III
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In embedded systems, off-chip buses and memory (i.e., L2 memory as opposed to the L1 memory which is usually on-chip cache) consume significant power often more than the processor itself. In this paper for the case of an embedded system with one processor chip and one memory chip, we propose frequency and voltage scaling of the off-chip buses and the memory chip and use a known micro-architectural enhancement called a store buffer to reduce the resulting impact on execution time. Our benchmarks show a system (processor + off-chip bus + off-chip memory) power savings of 28% to 36%, an energy savings of 13% to 35%, all while increasing the execution time in the range of 1% to 29%. Previous work in power-aware computing has focused on frequency and voltage scaling of the processors or selective power-down of sub-sets of off-chip memory chips. This paper quantitatively explores voltage/frequency scaling of off-chip buses and memory as a means of trading off performance for power/energy at the system level in embedded systems.

Published in:

System Synthesis, 2002. 15th International Symposium on

Date of Conference:

2-4 Oct. 2002