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The subcircuit identification (SI) is a task of recognition of instances of small subcircuits in a larger circuit. SI program are important components of CAD tools for the simulation, verification, and testing of ICs. Modern IC designs, first, contain millions of the nets and devices, and, second, thousands of subcircuits. The conventional SI algorithms based on the graph state-space search techniques are computationally demanding and may require long runtime for such ICs. In this paper, we develop an optimization-based graph recognition method for solving the SI problem. This method combines the self annealing optimization technique and two concepts from the pattern recognition theory, namely, the error propagation and the soft (delayed) decision making. In contrast to the search-based algorithms our method allows extremely fast simultaneous finding of all subcircuit instances. The experimental results show that it recognizes all the instances orders of magnitude faster than the search-oriented techniques.