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Embedded memory in system-on-chip design: architecture and prototype implementation

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2 Author(s)
Huang Jin ; Dept. of Electr. & Comput. Eng., Queen''s Univ., Canada ; Manjikian, N.

Advances in microelectronics fabrication technology have created new opportunities for system designers to employ embedded DRAM in system-on-chip (SoC) designs. This paper discusses an embedded DRAM architecture and its prototype implementation. The architecture consists of multiple memory banks, each with a row buffer to hold a subset of recently-accessed rows. The memory banks use either contiguous or interleaved addressing, and the row buffer in each bank uses either direct-mapping or full-associativity to map rows from the DRAM array into the buffer. A write bypass feature is also supported for the row buffer. A prototype memory bank implementation has been developed in VHDL for a programmable logic chip using embedded SRAM memory blocks to emulate a DRAM array. A single 256×256 memory bank uses only 4% of the logic capacity of a Xilinx XCV2000E chip and 10% of the embedded memory. Operational results demonstrate the functionality of the implementation for read and write accesses.

Published in:

Electrical and Computer Engineering, 2003. IEEE CCECE 2003. Canadian Conference on  (Volume:1 )

Date of Conference:

4-7 May 2003