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Advances in microelectronics fabrication technology have created new opportunities for system designers to employ embedded DRAM in system-on-chip (SoC) designs. This paper discusses an embedded DRAM architecture and its prototype implementation. The architecture consists of multiple memory banks, each with a row buffer to hold a subset of recently-accessed rows. The memory banks use either contiguous or interleaved addressing, and the row buffer in each bank uses either direct-mapping or full-associativity to map rows from the DRAM array into the buffer. A write bypass feature is also supported for the row buffer. A prototype memory bank implementation has been developed in VHDL for a programmable logic chip using embedded SRAM memory blocks to emulate a DRAM array. A single 256×256 memory bank uses only 4% of the logic capacity of a Xilinx XCV2000E chip and 10% of the embedded memory. Operational results demonstrate the functionality of the implementation for read and write accesses.