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Hardware-software co-synthesis of partially re-configurable embedded systems optimized for reduced power consumption

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4 Author(s)
J. Levman ; Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, Ont., Canada ; G. Khan ; J. Alirezaie ; K. Raahemifar

In this paper, we present a scheduling algorithm as part of the hardware-software co-synthesis of low power distributed embedded devices. We used a location priority based algorithm in order to address embedded computer systems consisting of processors, partially reprogrammable FPGAs, and other resources. Our proposed locality emphasized two-dimensional scheduling algorithm prioritizes the unused FPGA locations and chooses a task to match the given position. This is an unusual approach to task scheduling, where the norm is to prioritize the candidate pool of tasks and then decide on a location. The FPGA reconfiguration process consumes large amounts of power. This algorithm is optimized to reduce overall system power consumption and to ensure all tasks meet their respective deadlines. Preliminary experimental results reveal significant reconfiguration overhead reduction while maintaining a low deadline violation rate.

Published in:

Electrical and Computer Engineering, 2003. IEEE CCECE 2003. Canadian Conference on  (Volume:3 )

Date of Conference:

4-7 May 2003