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The three dimensional integration of active circuits, thinned or in standard thickness, into polymeric substrates challenges current substrate manufacturing processes in an unprecedented way. In order to overcome the risks associated with this 3D integration technology, the issues must be carefully studied and assessed. For the direct integration of ultrathin chips into dielectric build up layers of multi-layer printed circuit boards, such issues were identified and put to the test using advanced pcb manufacturing methods. Among the risks encountered in a manufacturing ambient Material selection (i)linear tolerance on a 18×12" board (ii)placement of ultrathin dice (iii)lamination process (iv)laser/plasma via formation (v)electroless deposition of seed layer (vi)patterning of the contact structures (vii)testing voltages were observed to be the ones affecting the outcome and will be discussed.