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This paper presents an improved master-slave bipolar Si-SiGe HBT comparator design for ultra-high-speed data converter applications. The latch is maintained during the track stage facilitating quick transition back to the latch stage, increasing the sampling speed of the comparator. Implemented in a 0.5-μm 55-GHz BiCMOS Si-SiGe process, this comparator consumes approximately 80 mW with sampling speeds up to 16 GHz.
Date of Publication: Sept. 2003