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Source/drain optimization of the dynamic-threshold DTMOS device in a 0.15 μm SOI embedded DRAM technology

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4 Author(s)
Burke, F. ; Dept. of Electr. & Comput. Eng., Boise State Univ., ID, USA ; Rambhatla, A. ; Zahurak, J. ; Parke, S.

This paper describes experimental results used to optimize the source/drain implant design of a dynamic threshold DTMOS n-channel device, fabricated within a low-cost 0.15 μm SOI CMOS System-On-Chip process, which also included high-density embedded DRAM. A shallower, lower dose S/D implant was found to lower the body resistance and DIBL, thus increasing the dynamic body effect. The DTMOS device design in this process was previously found to be superior to both grounded body (GB) and floating body (FB) operation, with Ion=56 uA/μm, Ioff=3 pA/μm, S=64 mV/dec, and Gm=1690 uS/μm at Vdd=1.0 V. This DTMOS device was also previously shown to have excellent analog and RF performance, with Fmax=32 GHz. These characteristics permit embedded ultra-low-voltage analog circuits and RF front-end circuits in combination with embedded DRAM cores for ultra-low-power, low-cost SOCs.

Published in:

University/Government/Industry Microelectronics Symposium, 2003. Proceedings of the 15th Biennial

Date of Conference:

30 June-2 July 2003

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