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In this paper, the threshold voltage of fully depleted silicon on insulator device with geometry scale down below 100 nm is investigated deeply. All the device simulations are performed using SILVACO Atlas device simulator. Several ways to control the threshold voltage are proposed and simulated. Threshold voltage changing with the silicon film thickness, channel doping concentration, gate oxide thickness and gate electrode work function is simulated. One short channel NMOS and one PMOS FDSOI device structure with effective channel length 90 nm and 30 nm silicon film thickness are designed.
Date of Conference: 30 June-2 July 2003