PLA optimization using output encoding

An automatic tool that heuristically determines a good partitioning of a single large programmable logic array (PLA) into a PLA with a smaller number of encoded outputs (and usually fewer product terms), followed by a set of decoders to regenerate the original outputs, has been developed. Initial results using logic descriptions of processor chips and a benchmark set of industrial PLAs show area savings of up to 35% and delay reductions of up to 45%. The approach can be considered an alternative to Boolean decomposition and factoring in multilevel logic synthesis.<
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