By Topic

Optimal CMOS cell transistor placement: a relaxation approach

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Stauffer, A. ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Nair, R.

A relaxation approach for producing a placement of transistors in a CMOS cell in a grid layout style from the circuit schematic diagram is described. For a given objective function, the approach leads to optimal results in most of the cases attempted. Unlike previous constructive approaches, this approach is iterative. It is also quite flexible. It can be used for unrestricted circuit types and can handle a variety of other important parameters affecting the wireability of the layout. The procedure is targeted for use in the automatic generation of custom and gate-array cell libraries.<>

Published in:

Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on

Date of Conference:

7-10 Nov. 1988