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Simulator-independent capacitance macro model for power DMOS transistors

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6 Author(s)

The paper presents an easy-to-use macro model for the gate-drain and gate-source capacitances of power DMOS transistors in VLSI smart power technologies according to T. Terashima (2002). The model is a capacitance model which can be used as an add-on to any existing DC SPICE model and with any SPICE simulator and can be derived directly form measurement data.

Published in:

Power Semiconductor Devices and ICs, 2003. Proceedings. ISPSD '03. 2003 IEEE 15th International Symposium on

Date of Conference:

14-17 April 2003