Simulator-independent capacitance macro model for power DMOS transistors

The paper presents an easy-to-use macro model for the gate-drain and gate-source capacitances of power DMOS transistors in VLSI smart power technologies according to T. Terashima (2002). The model is a capacitance model which can be used as an add-on to any existing DC SPICE model and with any SPICE simulator and can be derived directly form measurement data.