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S/D extension formation utilizing offset spacer for 65 nm node high performance CMOS

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3 Author(s)
K. Adachi ; SoC Res. & Dev. Center, Toshiba Corp. Semicon. Co., Kanagawa, Japan ; K. Ohuchi ; Y. Toyoshima

Source/drain extension engineering using a offset spacer for the 65 nm node high performance CMOS was investigated. Although a current drivability was degraded with increasing the offset spacer width, the improvement in the tolerance of short channel effect and the reduction of the overlap capacitance between the gate electrode and the source/drain extension were achieved. There exists an optimum spacer width from the AC performance viewpoint.

Published in:

Junction Technology, 2002. IWJT. Extended Abstracts of the Third International Workshop on

Date of Conference:

2-3 Dec. 2002