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Performance enhancements in BOLD using 'implications'

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4 Author(s)
Hachtel, G. ; Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA ; Jacoby, R. ; Moceyunas, P. ; Morrison, C.

Uses of implied network values or conditions in the context of multilevel logic synthesis are presented. The use of these implications has resulted in performance-enhanced versions, ESPRESSOMLT2 and MLTAUT2, of the two cornerstone tools of the BOLD system, ESPRESSOMLT (multilevel logic minimizer based on tautology checking) and MLTAUT (multilevel logic verifier). The relationship between the implied values and the intermediate don't care set is presented. Then it is shown how this relationship can be exploited to reduce the number of tautology calls and the number of leaves in the binary recursion tree of tautology checking. A parallelized version MLTAUT2P, which runs on a Sun 3/75 LAN, is discussed. ESPRESSOMLT2, is expected to have speedups of up to a factor of 20 and the parallelized version a factor of over 100.<>

Published in:

Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on

Date of Conference:

7-10 Nov. 1988

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