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Accelerated verification of RTL assertions based on satisfiability solvers

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5 Author(s)
Fraer, R. ; Logic & Validation Technol., Intel Corp., Haifa, Israel ; Ikram, S. ; Kamhi, G. ; Leonard, T.
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RTL assertions play an increasing role in the validation process. The high capacity and usability of Bounded Model Checking (BMC) make it especially attractive for the verification of such assertions. However, BMC is usually used to check a single property for a given bound, while here we are dealing with hundreds of properties each one requiring a different bound. We propose in this paper a new BMC algorithm that checks multiple properties simultaneously, and yet it is able to detect which properties failed or passed on an individual basis., Moreover, we show that our verification checks are stronger, as they can succeed in proving more properties than the classic algorithm.

Published in:

High-Level Design Validation and Test Workshop, 2002. Seventh IEEE International

Date of Conference:

27-29 Oct. 2002

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