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Functional verification is one of the most critical stages of microprocessor design. Its goal is to achieve the maximum level of confidence in the conformance of a processor design to its specification. A powerful methodology is necessary in order to cope with the major technical challenge which is posed by functional verification of a processor, and which stems from the vast state space that must be verified. This need becomes even more crucial when faced with the concurrent verification of several processor families. We describe a strategy for verification of several designs, which allows for maximum sharing of resources and knowledge among the verification projects, thus resulting in a significant increase in the efficiency of verification and in an associated reduction in the time required to verify a new design.